The design, testing, and fabrication of an integrated circuit (IC) is a complicated and expensive process. One goal of IC manufacturers and designers is to shorten the cycle time between design and fabrication to allow quick introduction of new ICs and quick production of application specific ICs (ASICs). To accomplish this goal in the most cost effective manner, chip designers and manufacturers rigorously test the IC design on computer simulations before fabrication. An effective testing program that verifies the IC design before fabrication returns dividends in lower production costs and higher chip yields.
The process to produce a new IC begins with a design, often performed with the aid of computer-aided design and manufacturing (CAD/CAM) technology. To verify the designs an automatic test pattern generator (ATPG) or other appropriate technology generates a set of test patterns that relate the external functionality of the IC to its internal state. The test patterns from the ATPG are loaded in parallel into various registers and components on a computer simulation of the IC to verify the function of the signal lines, combinatorial logic, registers, counters, and other IC elements and how they relate to the overall operation of the IC.
Once an IC has been manufactured, parallel loading of the test patterns into the IC is impossible. Thus, designs often incorporate testing circuitry, such as a scan chains that allows automated testing equipment (ATE) to scan in or serially load test patterns into internal registers or elements of the fabricated IC. Just as with the computer simulation, these test patterns set the IC to a known state. External inputs are then applied to the IC, and the scan chain allows the ATE to scan out or serially unload the resulting IC state for comparison with an expected state. The ATE serialized scan patterns may be generated from parallel ATPG test patterns. This parallel to serial conversion of test patterns is extremely important, and must take into account inversions and other logical manipulations along the scan chain to assure that the correct patterns are loaded for each test. If the conversion is done improperly or the original ATPG test patterns contain errors, flawless ICs may be rejected by the ATE because of an incorrect test pattern.
Therefore, from design to fabrication, an IC undergoes a variety of testing, including computer simulations using ATPG-generated test patterns and testing of the fabricated IC itself on an ATE using serialized scan patterns. Comprehensive testing of the IC design on a computer simulation or other testing tool before fabrication is relatively inexpensive, but often time consuming. The testing of the fabricated IC using serialized scan patterns validates the fabrication process, but can be expensive, especially when flaws in the IC design or serialized scan patterns were not discovered during computer simulation.